In integrated semiconductor memories, for example, DRAM (dynamic random access memory) semiconductor memories, operating parameters that determine the operating behavior of the integrated semiconductor memory are partly programmed into the semiconductor memory as early as in the production process. Such operating parameters relate to the setting of voltage values of an internal voltage network, the setting of delay parameters, and principally, also the activation of redundant structures.
FIG. 3 shows an integrated semiconductor memory 100 having a memory cell array 10. Within the memory cell array, memory cells SZ are arranged along word lines WL and bit lines BL. FIG. 3 illustrates in an exemplary manner a DRAM memory cell SZ comprising a selection transistor AT and a storage capacitor SC. In order to write an item of information to the memory cell or in order to read an item of information from the memory cell, the selection transistor AT is turned on by a corresponding control signal on the word line WL so that the storage capacitor SC is conductively connected to the bit line BL.
In the case of reading out an item of memory information, on the bit line BL, there is a potential increase or potential decrease relative to a precharge potential of the bit line, which is detected by a sense amplifier 11 and fed to an output terminal DQ of the integrated semiconductor memory in amplified fashion. When an item of information is read in, the signal level applied to the data terminal DQ is amplified by the sense amplifier 11 and written to the storage capacitor SC of the memory cell SZ via the bit line BL.
For controlling read and write accesses, the integrated semiconductor memory has a control circuit 40 and an address register 50. For selecting one of the memory cells SZ, a word line address X and a bit line address Y are applied to an address terminal A50. A memory cell of the memory cell array 10 is unambiguously identified based on the word and bit line addresses. When a control terminal S40 is driven with a write command WR, the memory cell array 10 is driven by the control circuit 40 such that a datum present at the data terminal DQ is written to the memory cell selected by the word and bit line addresses. If a read command RD is applied to the control circuit 40, the memory cell array 10 is configured by the control circuit 40 such that a memory cell SZ selected by the word line and bit line addresses is read at the data terminal DQ.
In the context of the production process, the memory cells along a word line are subject to extensive functional tests. If it is ascertained that defective memory cells are connected to a word line, or the word line itself has a defect, then the affected word line is generally replaced by a redundant word line WLr. Accordingly, the memory cells SZ connected to the defective word line WL are replaced by redundant memory cells SZr connected along the redundant word line WLR.
If a memory cell arranged along the defective word line is accessed during a read and write access, the control circuit 40 activates the redundant word line WLr, instead of the defective word line. For this purpose, the control circuit 40 must know the word line address X of the defective word line. If, for example, the word line WL is detected as defective in the production process or during subsequent testing, then the word line address X of the defective word line is stored in fuse elements of a fuse bank.
FIG. 3 shows five different fuse banks 21, 22, 23, 24, 25 at the edge of the memory cell array 10. The fuse banks are assigned to redundancy bit or word line decoders. The fuse banks are connected to read-out circuits 31, 32, 33, 34, 35 for the read-out of the respective fuse bank. The word line addresses of defective word lines that are programmed in the fuse banks are converted into a data record comprising a bit sequence B by the read-out circuits and forwarded to the control circuit 40. From activation of the integrated semiconductor memory, the control circuit 40 evaluates the bit sequences from the read-out circuits, so that the control circuit 40 then knows the addresses of the defective word lines.
FIG. 4 shows an enlarged illustration of the fuse bank 21 connected to the read-out circuit 31. The fuse bank 21 includes a plurality of fuse units 210, 220, 230, 240, 250, 260. Each of the fuse units illustrated in FIG. 4 includes fuse elements 0, . . . 7. The fuse elements may be formed as fusible links, for example, which are destroyed during programming in the production process by irradiation with a laser pulse. The respective programming state of the fuse element is detected by the read-out circuit 31. If, for example, when reading the fuse element 0 of the fuse unit 210, the read-out circuit 31 ascertains that the associated fusible link has been destroyed, this corresponds to a programming state “1,” for example. If, by contrast, the fusible link of the fuse element 0 has not been destroyed, this programming state corresponds to a logic “0.” It is possible, for example, for an address bit of a word line address assigned to a defective word line to be stored in a respective fuse element of a fuse unit. When the fuse unit 210 is read, the read-out circuit thus generates a bit sequence including address bits 0, . . . , 7 of the stored word line address.
Each of the fuse units 210, . . . , 260 illustrated in FIG. 4 is assigned a redundant structure, for example, a redundant word line, by a redundancy bit or word line decoder. For deciding whether a fuse unit contains a valid address of a defective word line, the respective fuse element 0 of a fuse unit is used as a signaling bit. If the fuse element 0 of the fuse unit 210 has the programming state “1”, for example, then the programming states of the fuse elements 1, . . . , 7 of the fuse unit 210 specify the address bits of the word line address X of the defective word line, which is replaced by the redundant word line assigned to the fuse unit 210.
The number of fuse elements of a fuse unit is dependent on the address range in which the redundant structure is intended to be used. However, each fuse element requires a considerable proportion of chip area CF. Reducing this proportion of the chip area becomes more desirable, the less the layout of the fuse elements can be reduced in size from memory generation to memory generation. The fuse elements are irradiated with high-energy radiation of a laser during programming. By virtue of the wavelength used, limits are imposed on arbitrarily reducing the size of the fuse elements in the context of scaling of the circuit layout. Relative to the rest of the circuit components, the fuse elements are thus occupying an ever larger space on the semiconductor chip.
The layout of the fuse elements with the associated read-out circuit has hitherto been positioned in proximity to the redundant structure. In order to configure the layout of a fuse bank in a manner as far as possible optimized with respect to area, fuse banks adjacent to one another are combined. The space taken up by necessary safety regions between a fuse bank and other circuit components of the integrated semiconductor memory can be reduced in this way. With dispersed redundant structures on the semiconductor chip, a further minimization of these safety zones is almost no longer possible at the present time.
In the unprogrammed state, the fuse elements of a fuse unit have the logic state “0.” Since the word line address X=0000000 of a defective word line cannot be distinguished from this presetting, instead of seven fuse elements, a total of eight fuse elements are used in the exemplary embodiment of FIG. 4. In this case, the fuse element 0, i.e., the master fuse, is no longer part of the word line address, but rather determines whether the redundant structure assigned to the fuse unit 210 is activated. Therefore, it no longer represents an address bit. If the fuse element 0 is programmed with the logic state “1,” for example, then the redundant word line assigned to the fuse unit 210, for example, is used instead of the regular word line, the word line address of which is determined by the programming state of the fuse elements 1, . . . , 7. This means that half of all programmable combinations of programming states of the fuse unit 210 are not utilized. Furthermore, at the present time, chip area is wasted, particularly, when the redundant structure is not used at all.
An integrated semiconductor memory in which the number of fuse elements required for programming operating settings of the integrated semiconductor memory is reduced, and a method for operating an integrated semiconductor memory in which the operating settings stored in a reduced number of fuse elements can be evaluated by a control circuit, are desirable.